The present invention relates to an autonomous timer for automatically resetting a central processing unit (CPU) or a microprocessor unit (MPU) used in a portable mobile telephone set, a portable transmitter-receiver or the like and, more particularly, to a control circuit for autonomous timers where a plurality of CPU's or MPU's are used in such a telephone set or the like.
Recently, telephone sets, transmitter-receivers or the like have come to be equipped with a plurality of CPU's or MPU's. As will be described in detail afterwards, each of these CPU's or MPU's is provided with an autonomous counter to reset itself when the CPU or MPU is in an abnormal condition. The autonomous counter functions as a timer. If no reset pulse is supplied from the CPU or MPU within a prescribed period of time, the timer judges that the CPU or MPU has been in an abnormal condition, and supplies an automatic reset pulse. The CPU or MPU generates the reset pulse every time it executes the task of a prescribed step. In a prior art control circuit for autonomous timers, the outputs of a plurality of autonomous counters are supplied to an OR gate, whose output resets all the CPU's or MPU's.
For a portable telephone set or transmitter-receiver, keeping all the CPU's or MPU's in operation would result in a waste of battery power. Therefore, one or more are constantly kept at work, but the rest are used intermittently only when needed. In this arrangement, the prior art control circuit for autonomous timers prevents the intermittently operating CPU's or MPU's from giving reset pulses to the autonomous timers within the prescribed period of time. As a result, even though all the CPU's or MPU's are functionally normal, the whole telephone set or transmitter-receiver would be suspended from operation.